The continuing push to produce faster semiconductor devices with lower power consumption has resulted in device miniaturization. In particular, smaller gate oxide thickness and silicon channel width are conducive to the low voltage and faster operation of transistor devices, such as complementary metal oxide (CMOS) transistors. With shrinking process geometries, the use of new manufacturing methods are being explored to further reduce power consumption and increase device switching speeds.
In a CMOS device, for instance, it has been found that incorporating a tensile stress into an N-type Metal Oxide Semiconductor (NMOS) transistor device increases electron mobility within the channel, and thereby, generally enhances transistor performance. This is presently accomplished by placing a tensile stress inducing layer over the NMOS device. This, in turn, allows the production of NMOS transistors having faster transistor switching speed and higher drive current. Typically, these layers have a thickness ranging from about 10 nm to about 120 nm.
Unfortunately, however, as design layouts have changed to meet the requirements for ever better transistor performance and greater speed, the use of such layers have begun to meet design limitations regarding the amount of stress that can be incorporated into the channel. For example, while a layer thicker than those presently being used could induce greater tensile stress in the channel, the use of such thicker layers is limited by design layout. This is particularly the case as component density has increased, which has caused a narrower spacing between the poly lines that form the transistor gates. When a thicker layer is used on such narrowly spaced devices, there is a resulting “pitch effect”. The narrower spacings between the poly lines enhances the local stress to such an extent that the dopant diffusions of adjacent transistor structures can overrun each other, which, in turn, can cause transistor malfunction or complete transistor failure.
In addition to the problem associated with the narrower spacing, layer thickness is also limited due to hydrogen incorporation from the film into adjacent P-type Metal Oxide Semiconductor (PMOS) devices. Depending on the type of layer used, a substantial amount of hydrogen can become incorporated into the PMOS device during the layer's deposition or simply by diffusion from the layer to such an extent that it can actually “kill” the PMOS device.
Thus, due to the beneficial effects that tensile stress has on a device's performance, it would be highly desirable to increase the tensile stress within a transistor device. Unfortunately, however, the amount of stress, which is proportional to the layer's thickness, is presently limited by design layout or by its effects on adjacent PMOS devices.
Accordingly, what is needed is a method for incorporated additional tensile stress into an NMOS device that is not affected by design layout or the presence of PMOS devices.